Chroma Expansion Board: Technicalby Sandro Sfregola  <firstname.lastname@example.org>
with David Clarke [21030085++] <email@example.com>
The CEB was the precursor of the CPU Plus (CC+), implementing the initial functionality of the CC+ as an add-on rather than a replacement board. The information on these pages is provided for historical interest; there will be no further updates or firmware revisions. See The Chroma CPU Plus (CC+).
The circuit is quite "simple": a 32 KB EPROM (27C256), a 8 KB low power static RAM (6264LP), a very common UART (16C550), a fast optocoupler (6N139) and some "glue" logic (one 74HC14 and one 74HCT02). Here are the schematics:
ROMThe /ROM signal selects U1, a 27C256 EPROM; this signal is the inverted A15 line from CPU, by U4C gate (74HCT02). This arrangement maps the ROM area at $8000 - FFFF. The W/R signal enables the EPROM output buffer during data transfers to the CPU.
The /RAM signal selects U2, a 6264LP static RAM; this signal comes from an unused output of Z7 on CPU board, pin 13, mapping the RAM at $4000 - $5FFF; the other chip select, CS2, is connected to the /RESET signal providing power-off low supply current and data integrity in every condition; the W/R signal enables the RAM output buffer during data transfers to the CPU while the R/W signal allow the CPU to write data to the RAM. U2 supply is the same of the original Chroma CMOS RAM (battery backup).
The three lowest address lines, A0 - A1 - A2 select one of the eight internal U3 register; data transfers to and from this register are enabled by RD and WR signals obtained by gates U4A - U4B; the /UART signal comes from an unused output of Z7 on CPU board, pin 12, mapping the UART at $6000 - $6007.
An active high reset signal (RES) is provided by U5F and applied to U3 master reset pin 35.
To reduce radiated noise, a local clock is generated by U3 itself by a 4 MHz crystal; this clock is internally divided providing the MIDI baud rate of 31250 (31250 * 8 * 16).
The CPU IRQ hardware interrupt is originally used for Chroma port data transfers; here this interrupt is shared in the following way: the connection between Z11 pin 6 and Z1 pin 3 (CPU /IRQ input) is opened and the two circuit points connected to the expansion board; Z11 pin 6 becomes the /IOINT signal (J3 - 8) while Z1 pin 3 becomes /CPUINT (J3 - 9). An unmasked Chroma port interrupt causes the /IOINT signal to go low; this signal is inverted by U5C, becoming IOINT, and applied to one input of a NOR gate (U4D); the active high interrupt request signal from UART, UINT, goes to the other input of the same gate so whatever interrupt occur, Chroma port or UART, the /CPUINT signal goes low causing an IRQ request to CPU. The IOINT signal is also connected to an aux input of the UART (/CTS, pin 36) so the firmware IRQ servicing routine can easily detect which kind of interrupt is pending (port, UART or both). Since Z11 is TTL and U5 an Schmitt trigger input 74HC part, a pull-up resistor (R1) is used.
UART: Serial I/O - MIDI interface
The MIDI input serial stream at OPTO1 pin 6 is applied to U5A; since the optocoupler is linear enough to pass noise from the MIDI line, a Schmitt trigger device in the circuit improves noise immunity; the signal is inverted again by U5B before the UART serial input.
The UART serial output drives the MIDI output by the usual couple of inverters (U5E, U5D) and R4, R5.
UART: Auxiliary circuits
A triple DIP switch is connected to UART aux inputs /DSR, /RI and /DCD; the firmware can access the status of these switches for various purposes (see special modes).
UART outputs /OUT1 and /OUT2 are buffered by Q1 and Q2 providing enough current for LED indicators.
F1 gives protection in the case of a short from J5 - 1 (+5) to ground.
As you can see in the pictures, I have built the circuit on a pre-drilled board.
U1 27C256 EPROM: access time =< 250nS will work (current slower devices are 150nS or better)
U2 6264LP RAM: see U1 for access time, different part names from various brands have the same function and will work
U3 16C550 UART: with B or higher suffix (C, D etc.); "A" parts are too slow for MIDI
U4 and U5: standard 74HC parts
OPTO1 6N139: this is the improved version of the 6N138; since it is almost unused by the MIDI industry, this little friend cost less and perform better
R1 - R14: standard 1/4 W 1% metal film resistors
C2 - C6: bypass ceramic multilayer capacitors (Z5U or equivalents)
C1: electrolytic aluminium capacitor, 105°, 16V
C7 - C8: ceramic disk capacitors
CR1: miniature 4 MHz crystal
J1 - J2: gold plated IC sockets
J3 - J5: AMP gold plated 90° male PCB connectors
F1: small chip fuse
I recommend good gold plated sockets for all the IC.
The Chroma computer board must be removed from the instrument for the CEB installation; before that pull the two memory backup batteries.
A 24 wires flat cable does most of the connections between the CEB and the CPU board; this cable (and all the other signal wires) must be as short as possible (see pictures). I have used another 16 wires flat cable to connect J2 to a socket in place of Z5 on CPU board; another option is: left Z5 in place, replace J2 with a 3-pole connector and run 3 wires to the relative Z5 pins.
Of course all the eight original firmware EPROM must be pulled from the sockets before the installation of the expansion board!
The following wires complete the connection between boards:
|J3 - 1||to Z7 pin 2|
|J3 - 2||to Z7 pin 3|
|J3 - 3||to Z7 pin 13|
|J3 - 4||to Z3 pin 3|
|J3 - 5||to any point of the /RESET line (a good point is R1)|
|J3 - 6||to any point of the CMOS RAM supply (from Q1 collector)|
|J3 - 7||to Z7 pin 12|
|J3 - 8||to Z11 pin 6|
|J3 - 9||to Z1 pin 3* (see note)|
|J3 - 10||none|
* To break the original connection without cutting traces, pull Z1 out of the socket; gently bend pin 3 and reinsert Z1 on the socket so the pin remains unconnected; solder the wire from J3 - 9 to Z1 pin 3.
Instead of punching holes on the rear of the Chroma, I have put a DB9 female connector on the free slot beside the existing Chroma port DB25; I have built a small box provided with a short cable and a DB9 male connector; the box hosts the two 5-pole DIN female connectors (MIDI IN and OUT) and the two LED (see the following diagram for wiring).
As an alternative to the box, a simple Y cable could be made.
Note: LED 1 is the default MIDI IN activity indicator.
It is better to check carefully all the connections. Once you have programmed the EPROM with the provided firmware put it on the relative socket. Set all the DIP switches to OFF position. Put the two memory backup batteries in place.
At power on, the Chroma must boot up as usual; if not turn the power off immediately and recheck all.
If everything is OK, enter the MIDI user interface with Set Split: 36 and set the various parameters as you like then exit pressing 36 again (remember that these parameters are lost every time you replace the batteries as your sound programs).
Then you can connect your PC, load a sound bank via sysex and play the Chroma from your favourite sequencing program.
Enjoy (and check the site for firmware updates)!